KittyAsm.hpp

#pragma once
 
#include <cstdint>
#include <cstdio>
#include <string>

enum class EKittyArmCond : uint8_t
{
    EQ, NE, HS, LO, MI, PL, VS, VC, HI, LS, GE, LT, GT, LE, AL, NV,
    None,
};

enum class EKittyInsnTypeArm32
{
    UNKNOWN,

    ADR,

    ADR_REG,
 
    ADD, 
    SUB, 

    SUB_SP_IMM,
 
    MOV_IMM,     
    MOV_REG,     
    MOV_SHIFTED,
 
    LDR,  
    STR,  
    LDRB, 
    STRB, 
    LDRH, 
    STRH, 
    LDRSB, 
    LDRSH, 

    LDR_LITERAL,

    LDR_PC_REG,
 
    B,      
    BL,     
    B_COND, 
    BX,     
    PUSH_SP,
    POP_PC,
    MOVW,
    MOVT,

    COUNT,
};

struct KittyInsnArm32
{
    EKittyInsnTypeArm32 type;

    int rd = -1, rn = -1, rt = -1;
    uint32_t word;    
    uint32_t address; 
    int32_t immediate;
    uint32_t target;
    EKittyArmCond cond = EKittyArmCond::None;

    bool writeback;

    bool postIndexed;

    bool registerOffset;

    bool shiftedOperand;

    bool subtractsOffset;

    bool registerForm;

    bool pcRelative;
 
    KittyInsnArm32()
        : type(EKittyInsnTypeArm32::UNKNOWN), word(0), address(0), immediate(0), target(0),
          writeback(false), postIndexed(false), registerOffset(false), shiftedOperand(false),
          subtractsOffset(false), registerForm(false), pcRelative(false)
    {
    }

    inline bool isValid() const
    {
        return word != 0 && type != EKittyInsnTypeArm32::UNKNOWN;
    }

    std::string ToString() const;
};

enum class EKittyInsnTypeArm64
{
    UNKNOWN,
 
    ADR,  
    ADRP,
 
    ADD,  
    SUB,  
 
    MOVZ, 
    MOVN, 
    MOVK,
 
    // ── Scaled immediate-offset load/store ────────────────────────────────────
    // The width is carried by the *type*, not by a field, so each width is its
    // own value. Folding any of them together reports the wrong access size, and
    // access size is what separates a pointer field from a counter.
 
    LDR,   
    STR,   
    LDRW,  
    STRW,  
    LDRB,  
    STRB,  
    LDRH,  
    STRH,  
    LDRSB, 
    LDRSH, 
    LDRSW,
 
    // ── Pre-indexed (writeback before the access) ─────────────────────────────
    // `[Xn, #imm]!` - the offset is applied to Xn *and* kept. A consumer tracking
    // register values has to invalidate Xn, which `writeback` reports.

    LDR_PRE,
    STR_PRE,
    LDRW_PRE,
    STRW_PRE,
    LDRW_POST,
    STRW_POST,
    LDRB_PRE,
    STRB_PRE,
    LDRH_PRE,
    STRH_PRE,
    LDRSB_PRE,
    LDRSH_PRE,
    LDRSW_PRE,
 
    // ── Post-indexed (writeback after the access) ─────────────────────────────
    // `[Xn], #imm` - the access happens at [Xn] and the immediate is applied
    // afterwards, so the immediate is *not* an access offset. Reading it as one
    // places the access at an address the program never formed, which is what
    // `postIndexed` exists to prevent.

    LDR_POST,
    STR_POST,
    LDRB_POST,
    STRB_POST,
    LDRH_POST,
    STRH_POST,
    LDRSB_POST,
    LDRSH_POST,
    LDRSW_POST,
 
    // ── Unscaled immediate offset (LDUR / STUR) ───────────────────────────────
    // Same widths again, but the 9-bit offset is signed and *unscaled*, where the
    // LDR/STR forms scale theirs by the access size. Same access, different
    // immediate encoding - which is exactly why they cannot share a type.

    LDUR,
    STUR,
    LDURW,
    STURW,
    LDURB,
    STURB,
    LDURH,
    STURH,
    LDURSB,
    LDURSH,
    LDURSW,
 
    // ── PC-relative literal loads ─────────────────────────────────────────────
    // `LDR Xt,label` - reads the word *stored at* a PC-relative address, so
    // `target` is the slot and the register receives its contents.
 
    LDR_LITERAL,   
    LDRW_LITERAL,  
    LDRSW_LITERAL, 
 
    B,      
    BL,     
    B_COND, 
    CBZ,    
    CBNZ,   
    TBZ,    
    TBNZ,   
    RET,
    STP_PRE_SP,
    SUB_SP_IMM,
    MOV,

    COUNT,
};

struct KittyInsnArm64
{
    EKittyInsnTypeArm64 type = EKittyInsnTypeArm64::UNKNOWN;

    int rd = -1, rn = -1, rt = -1;
    int rm = -1;
    uint32_t word;    
    uint64_t address; 
    int64_t immediate; 
    int64_t bitpos;    
    uint64_t target;   
    EKittyArmCond cond = EKittyArmCond::None;

    bool writeback;

    bool postIndexed;

    bool registerOffset;
 
    KittyInsnArm64()
        : type(EKittyInsnTypeArm64::UNKNOWN), word(0), address(0), immediate(0), bitpos(0),
          target(0), writeback(false), postIndexed(false), registerOffset(false)
    {
    }

    inline bool isValid() const
    {
        return word != 0 && type != EKittyInsnTypeArm64::UNKNOWN;
    }

    std::string ToString() const;
};

namespace KittyAsm
{
    uint32_t bits(uint32_t v, int hi, int lo);

    inline bool bit(uint32_t v, int pos)
    {
        return bits(v, pos, pos) != 0;
    }

    inline uint8_t ror8(uint8_t value, unsigned int shift)
    {
        shift &= 7u;
        return static_cast<uint8_t>((value >> shift) | (value << ((8 - shift) & 7u)));
    }

    inline uint8_t rol8(uint8_t value, unsigned int shift)
    {
        shift &= 7u;
        return static_cast<uint8_t>((value << shift) | (value >> ((8 - shift) & 7u)));
    }

    inline uint16_t ror16(uint16_t value, unsigned int shift)
    {
        shift &= 15u;
        return static_cast<uint16_t>((value >> shift) | (value << ((16 - shift) & 15u)));
    }

    inline uint16_t rol16(uint16_t value, unsigned int shift)
    {
        shift &= 15u;
        return static_cast<uint16_t>((value << shift) | (value >> ((16 - shift) & 15u)));
    }

    inline uint32_t ror32(uint32_t value, unsigned int shift)
    {
        shift &= 31u;
        return (value >> shift) | (value << ((32 - shift) & 31u));
    }

    inline uint32_t rol32(uint32_t value, unsigned int shift)
    {
        shift &= 31u;
        return (value << shift) | (value >> ((32 - shift) & 31u));
    }

    inline uint64_t ror64(uint64_t value, unsigned int shift)
    {
        shift &= 63u;
        return (value >> shift) | (value << ((64 - shift) & 63u));
    }

    inline uint64_t rol64(uint64_t value, unsigned int shift)
    {
        shift &= 63u;
        return (value << shift) | (value >> ((64 - shift) & 63u));
    }

    inline uint16_t swap16(uint16_t value)
    {
        return static_cast<uint16_t>((value >> 8) | (value << 8));
    }

    inline uint32_t swap32(uint32_t value)
    {
        return ((value & 0x000000FFu) << 24) |
               ((value & 0x0000FF00u) << 8)  |
               ((value & 0x00FF0000u) >> 8)  |
               ((value & 0xFF000000u) >> 24);
    }

    inline uint64_t swap64(uint64_t value)
    {
        return ((value & 0x00000000000000FFull) << 56) |
               ((value & 0x000000000000FF00ull) << 40) |
               ((value & 0x0000000000FF0000ull) << 24) |
               ((value & 0x00000000FF000000ull) << 8)  |
               ((value & 0x000000FF00000000ull) >> 8)  |
               ((value & 0x0000FF0000000000ull) >> 24) |
               ((value & 0x00FF000000000000ull) >> 40) |
               ((value & 0xFF00000000000000ull) >> 56);
    }

    inline std::string toHexString(uint64_t v)
    {
        char Buf[20];
        std::snprintf(Buf, sizeof(Buf), "0x%llX", static_cast<unsigned long long>(v));
        return Buf;
    }
} // namespace KittyAsm

namespace KittyArm32
{
    // ──── Constants ───────────────────────────────────────────────────────────

    constexpr uint32_t kInstructionStride = 4;

    constexpr uint32_t kPcBias = 8;

    constexpr int kLinkRegister = 14;

    constexpr int kNumGPRegisters = 15;
 
    // ──── Bit helpers ─────────────────────────────────────────────────────────

    inline int32_t signExtend(uint32_t val, int bits)
    {
        // Guarded against the field's own width, not the ARM64 twin's: `m` is
        // 32-bit here, so a shift landing at bit 32 or above would compute a
        // value the narrowing conversion silently reduces to 0, leaving the
        // out-of-range guard doing nothing to earn its keep.
        if (bits <= 0 || bits >= 32)
            return (int32_t)val;
 
        uint32_t m = 1u << (bits - 1);
        return (int32_t)((val ^ m) - m);
    }
 
    // ──── Register naming and indexing ────────────────────────────────────────

    inline std::string regName(unsigned r)
    {
        if (r == 13)
            return "sp";
        if (r == 14)
            return "lr";
        if (r == 15)
            return "pc";
 
        std::string reg = "r";
        return reg + std::to_string(r);
    }

    int regIndex(const std::string &name);

    inline std::string branchCondName(uint32_t cond)
    {
        // Masked, not rejected: the condition is a 4-bit field and callers pass
        // it straight out of the instruction word, so anything above 15 is a
        // caller error rather than a distinct condition. Masking keeps the
        // lookup in range for every possible input.
        static const char *names[16] =
            {"EQ", "NE", "CS/HS", "CC/LO", "MI", "PL", "VS", "VC", "HI", "LS", "GE", "LT", "GT", "LE", "AL", "NV"};
        return names[cond & 0xF];
    }
 
    // ──── Instruction classification ──────────────────────────────────────────

    std::string typeToString(EKittyInsnTypeArm32 t);

    uint8_t loadStoreWidth(EKittyInsnTypeArm32 t);

    bool isLoad(EKittyInsnTypeArm32 t);

    bool isStore(EKittyInsnTypeArm32 t);
 
    // ──── Decoding ────────────────────────────────────────────────────────────

    EKittyInsnTypeArm32 decodeInsnType(uint32_t instr);

    KittyInsnArm32 decodeInsn(uint32_t instr, uint32_t address = 0);
 
} // namespace KittyArm32
 

namespace KittyArm64
{
    // ──── Constants ───────────────────────────────────────────────────────────

    constexpr uint32_t kInstructionStride = 4;

    constexpr int kNumGPRegisters = 32;
 
    // ──── Bit helpers ─────────────────────────────────────────────────────────

    inline int64_t signExtend(uint32_t val, int bits)
    {
        if (bits <= 0 || bits >= 64)
            return (int64_t)val;
 
        uint64_t m = 1ULL << (bits - 1);
        return (int64_t)((val ^ m) - m);
    }
 
    // ──── Register naming and indexing ────────────────────────────────────────

    enum class EZeroRegOrStackPointer
    {
        ZeroRegister, 
        StackPointer, 
    };

    inline std::string xRegName(unsigned reg, EZeroRegOrStackPointer at31)
    {
        if (reg == 31)
        {
            return at31 == EZeroRegOrStackPointer::StackPointer ? "SP" : "XZR";
        }
        return std::string("X") + std::to_string(reg);
    }

    inline std::string wRegName(unsigned reg, EZeroRegOrStackPointer at31)
    {
        if (reg == 31)
        {
            return at31 == EZeroRegOrStackPointer::StackPointer ? "SP" : "WZR";
        }
        return std::string("W") + std::to_string(reg);
    }

    inline int resolveRegIndex(unsigned reg, EZeroRegOrStackPointer at31)
    {
        if (reg == 31)
            return at31 == EZeroRegOrStackPointer::StackPointer ? 31 : -1;
        return static_cast<int>(reg);
    }

    int regIndex(const std::string &name);

    inline std::string branchCondName(uint32_t cond)
    {
        static const char *names[16] =
            {"EQ", "NE", "HS", "LO", "MI", "PL", "VS", "VC", "HI", "LS", "GE", "LT", "GT", "LE", "AL", "NV"};
        uint32_t index = cond & 0xF;
        return index < 16 ? names[index] : "";
    }
 
    // ──── Instruction classification ──────────────────────────────────────────

    std::string typeToString(EKittyInsnTypeArm64 t);

    uint8_t loadStoreWidth(EKittyInsnTypeArm64 t);

    bool isLoad(EKittyInsnTypeArm64 t);

    bool isStore(EKittyInsnTypeArm64 t);
 
    // ──── Decoding ────────────────────────────────────────────────────────────

    EKittyInsnTypeArm64 decodeInsnType(uint32_t instr);

    KittyInsnArm64 decodeInsn(uint32_t instr, uint64_t address = 0);
 
} // namespace KittyArm64